1. Field of the Invention
The present invention relates to semiconductor devices. More particularly, the present invention relates to field effect transistors such as metal-oxide-semiconductor field effect transistors.
2. Description of the Related Art
Both fully silicided (FUSI) gate structures and embedded silicon germanium (eSiGe) structures have shown usefulness in enhancing the performance of field effect transistors (FET), particularly MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). However, techniques for manufacturing both FUSI and eSiGe structures involve processes that are highly complex when compared to typical CMOS (Complementary Metal Oxide Semiconductor) manufacturing processes.
In addition to typical CMOS processes, fully siliciding the gates of a FET requires additional etching steps, and may require additional chemical mechanical polishing (CMP) steps as well. For example, current FUSI manufacturing techniques require steps of etching and polishing the conductive gate layers prior to silicidation.
Likewise, embedded silicon germanium (eSiGe) structures require additional manufacturing steps. In addition to processes required to form recesses in the FET source and drain regions, and processes to grow the embedded SiGe regions in the recesses, the eSiGe process requires additional steps in order to protect the gates during growth of the eSiGe region.